Education
1995/07:East China University of Technology Photo Electronics: Master
1992/09: East China University of Technology Photo-Electronics: Bachelor

Certifications
1999/10 Certified Advanced Programmer

Language Skills
English             CET-6        skilled

IT Skills
Skill Name                    Skill Level
--------------------------------------------------------
Visual C++                        skilled
Embedded Systems            Expert
Linux                                 skilled
Firmware                           skilled
RTOS Porting                     skilled
Telecom Application           skilled

Miscellaneous Info
Special technical skills:
(1) Familiar with Embedded System Firmware design:
8-bit MCU:   AT89C52/MC68HC11/W6502
16-bit MCU: ATMEL AVR (AT90S8515);
32-bit MCU:

IDT MIPS ==> IDT 79RC32332/334;

Intel XScale ==>PXA255, PXA271;
Good at MIPS/XScale BootLoader/BSP design and RTOS porting (uC/OS-II, Nucleus, VxWorks, uCLinux);

(2) Familiar with the CPLD/FPGA application, use Maxplus2/Quatus to implement logic design and Simulation with schematic or Verilog HDL codes;
Often use EPM7128(EPLD) & 10K50E/EPM6016( FPGA );

(3) Familiar with the EDA tool includes Protel98/99SE and PSPICE, good at PCB layout(4 Layers) and PSPICE analyze the analogue circuit;

(4) Familiar with Visual C++ MFC programming, design & release the MIPS Generic Toolkits Software for Chip validation ( such as JET/Framer) via UART/EPP port;

(5) Familiar with GNU Tool Chain, include Make, GCC Compiler , Linker & GDB Debug for Target MPU (MIPS/Xscale); 

Covered Projects:
2003/11--Present：Intel Cloudcroft Test Engine
Software Environment: Intel Nordheim IDE & C/C++ Compiler
Hardware Environment: Intel Lubbock/MainStone-II
Development Tools: Intel Nordheim IDE & Nucleus Plus RTOS
Project Description: Design Test Engine for Cloudcroft Flash file system test, use Intel Nordheim IDE debug and porting Nucleus RTOS to XScale(PXA255/PXA271) MPU. Multi-thread oriented tasks for download/log/mirror test, support Ethernet and remote control via Flower-tracer.
Responsibility: Be in charge of Target Board debug and Target Application design, porting Nucleus to Xscale MPU and do real time test, write document for SAS/HLD/LLD and System Architecture Review. Design major codes for Target side with remote control via Nucleus TCP/IP stack protocol, implement XIP codes of Remote online burn image for Intel FFS, provide powerful FTA tool to Intel System group for Flash device function validation.

2003/03--2003/11：IDT MIPS Test Bench
Software Environment: SDE-MIPS Compiler Hardware Environment: MIPS Control Board
Development Tools: Wind-River VisionClick ICE & uC/OS-II kernel
Project Description: Write BSP for MIPS Control Board and override the runtime library for MIPS Test Bench, porting uC/OS-II to IDT MIPS 79RC32332/334 MPU, Design Generic MIPS Toolkit for FPGA dynamic configure, Binary C Code download and real time test, run multi-task on uC/OS-II for HDLC & SIGX testing.
Responsibility: Design MIPS BSP & Debug, include SDRAM module, UART, USB, Override the library for printf()/malloc(),.etc, release MIPS Tool-Kit for real-time testing, porting uC/OS-II to MIPS MPU.

2002/03--2003/3：Octal Framer/Transceiver
Software Environment: SDE-MIPS Compiler
Hardware Environment: MIPS Control Board & Backplane
Development Tools: uC/OS-II & MFC Design dynamic script & Tcl script for test case; Design real time test code for IC Chip function validation on FPGA Emulation platform, run HDLC/SIGX testing for regression test.
Responsibility: Design & Debug MIPS BSP, Write test code for tcl script & real time function validation, log the test report and find the root cause.


Selected Honors:
(1) Play a key role for Caller ID chip system validation for IDT-Newave, Design the evaluation board schematic/PCB Layout & Test codes for BellCore Test, System support for this chip which sell more than 10 millions of parts for IDT,  own the crystal prize of IDT-Newave; (Our team: 2 Analogue /2 Digital IC designers/2 System Engineer & Silicon Layout made the success story in IDT.)

(2) I am in charge of IDT MIPS Test Bench design project, which support digit TeleCom chip function validation for IDT-Newave, define the system architecture & implements MIPS 79RC32334 BSP & Low level code, provide total solution as generic MIPS Tool-Kit with VC++ GUI for multi-task scheduler of uC/OS-II, make a successful story in IDT-Newave; This MIPT Test Bench used as the digit IC validation platform for IDT-Newave, such as Octal Framer/Transceiver/SPI Bridge Chip.

(3) Obtained the qualification & Rank level certification of Advanced Software Engineer approved & issued by Ministry of PRC;