Karthik Chandrasekar
Computer Engineering, Delft University of Technology
Journals, Conferences and Workshops
[1] Venkateswaran Nagarajan, Karthik Chandrasekar et al “Towards Node Architecture Designs for Realizing High Productivity Supercomputers” presented at the 23rd International Supercomputing Conference (ISC) 2008, Dresden, Germany in Jun ’08.
[2] Venkateswaran Nagarajan, Karthik Chandrasekar et al “On the Concepts of Simultaneous Execution of Multiple Applications on the Hierarchically based Cluster and the Silicon Operating System” presented at Large-Scale Parallel Processing workshop held at the 22nd IEEE IPDPS ’08, Miami, USA, in Apr ’08.
[3] Venkateswaran Nagarajan, Karthik Chandrasekar and Shrikanth Ganapathy “Design for Testability of Functional Cores in High Performance Node Architectures” presented at DELTA 2008, the 4th IEEE International Symposium on Electronic Design, Test & Applications, Hong Kong, China, in Jan ‘08.
[4] Venkateswaran Nagarajan, Karthik Chandrasekar et al "Future Generation Supercomputers I: A Paradigm for Node Architecture" published as a regular contribution in ACM SIGARCH Computer Architecture News, Vol.35, Issue #5, Dec '07.
[5] Venkateswaran Nagarajan, Karthik Chandrasekar et al "High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications" presented at the Low Power Design workshop at the 8th MAPLD Conference by NASA, Washington D.C, in Sep ‘05.
[2] Venkateswaran Nagarajan, Karthik Chandrasekar et al “On the Concepts of Simultaneous Execution of Multiple Applications on the Hierarchically based Cluster and the Silicon Operating System” presented at Large-Scale Parallel Processing workshop held at the 22nd IEEE IPDPS ’08, Miami, USA, in Apr ’08.
[3] Venkateswaran Nagarajan, Karthik Chandrasekar and Shrikanth Ganapathy “Design for Testability of Functional Cores in High Performance Node Architectures” presented at DELTA 2008, the 4th IEEE International Symposium on Electronic Design, Test & Applications, Hong Kong, China, in Jan ‘08.
[4] Venkateswaran Nagarajan, Karthik Chandrasekar et al "Future Generation Supercomputers I: A Paradigm for Node Architecture" published as a regular contribution in ACM SIGARCH Computer Architecture News, Vol.35, Issue #5, Dec '07.
[5] Venkateswaran Nagarajan, Karthik Chandrasekar et al "High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications" presented at the Low Power Design workshop at the 8th MAPLD Conference by NASA, Washington D.C, in Sep ‘05.
Undergraduate Thesis - WAran Research FoundaTion (WARFT)
[6]
“Design Verification of Memory In Processor Super Computer On a Chip”,
dealing with Design of Memory in Processor Architecture, its ISA and
Functional Units, submitted to Waran Research Foundation in partial
fulfillment of the requirements for the Research Training program, in
Aug ’07.
Undergraduate Final Year Thesis Project - Anna University
[7] “Simulated Annealing-based Multiple-width Global Interconnect Routing”, submitted to SSN College of Engineering, Anna University in partial fulfillment of the requirements for the Degree of Bachelor of Engineering, in Computer Science and Engineering, in May ’06.
Technical Reports
Internal reports - published and presented at “Dhi Yantra ’06”, WARFT Workshop on “Brain Modeling & Supercomputing”, Chennai, India, in Mar ’06
[8] Venkateswaran Nagarajan, Karthik Chandrasekar et al “Memory and Power Efficient Application Execution In MIP SCOC”
[9] Venkateswaran Nagarajan, Karthik Chandrasekar et al “A White Paper on Memory In Processor SuperComputer On a Chip Architecture” – Part I
[10] Venkateswaran Nagarajan, Karthik Chandrasekar et al, “A White Paper on Memory In Processor SCOC Cluster Architecture” – Part II
[8] Venkateswaran Nagarajan, Karthik Chandrasekar et al “Memory and Power Efficient Application Execution In MIP SCOC”
[9] Venkateswaran Nagarajan, Karthik Chandrasekar et al “A White Paper on Memory In Processor SuperComputer On a Chip Architecture” – Part I
[10] Venkateswaran Nagarajan, Karthik Chandrasekar et al, “A White Paper on Memory In Processor SCOC Cluster Architecture” – Part II
