Karthik Chandrasekar

I am pursuing my MSc in Computer Engineering at the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) at Delft University of Technology (TU Delft), The Netherlands. My research interests include Processor Microarchitecture, On-Chip Interconnection, Multi-core and System On Chip Architectures, Reconfigurable Architectures and Embedded Systems.

I am currently working on Functional and Performance Validation of Network On Chip architectures for my Masters graduation thesis at the Integrated Systems Laboratory (LSI) at Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland.

During Aug '08 - Oct '08, I did my internship at LSI (EPFL), where I worked on Characterization and Optimization of Network-on-Chips on FPGAs. During Feb '07 - Aug '07,  I worked as a research associate, at Waran Research Foundation (WARFT), Chennai, India, as a member of their High Performance Computing group till Aug '07.  The primary focus of my work was Design Verification and HDL simulation for the MIP SCOC (Memory in Processor Super Computer on a Chip). I had also worked part-time, as a research trainee from Aug '04 to Aug '06, in a 2 year research training program at WARFT, where I was involved in the Micro-architectural design of the MIP SCOC. I received my Bachelor Of Engineering (B.E.) Degree in Computer Science and Engineering (with Distinction) from Anna University, India in Jun '06.