ASIC Development:

- Design: Verilog/VHDL, Schematic Capture

- Synthesis: Synopsys, Cadence, Mentor

- Simulation: NC-Verilog, Verilog-XL, Modelsim

- Timing Analysis: Primetime

- Test Insertion: Scan, JTAG, can handle multiple clock issues

- ASIC Vendor Interface

- Methodology Development

FPGA Development:

- Design: Verilog/VHDL, Schematic Capture

- Synthesis: Synplicity, Mentor, Synopsys

- Simulation and Verification

- Testability

- Post Place & Route Verification

- Methodology Development

- FPGA to ASIC Conversion

- Xilinx, Altera, Actel

We can provide any or all of the services listed above.