"Many times the difference between failure and success is doing something nearly right...

or doing it exactly right."

We have over 18 years of experience in ASIC and FPGA development.  Complete knowledge of the entire ASIC design flow with particular strengths in ASIC methodology and ASIC vendor interface. We also have extensive experience in the area of ASIC development tools (Synthesis, Timing Analysis, Simulation and Testability).   

Proficiency       

• ASIC, FPGA design, applications and Methodologies
• UNIX, PC-NT, Windows, Teradyne Testers
• Synopsys Test Compiler, Design Compiler, Primetime
• Cadence Verilog, Ambit Buildgates
• Mentor Leonardo Spectrum, Modelsim
• Novas Debussy, Transeda Code Coverage